We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34297

11.4 EDK, MPMC - "ERROR:Place:901 - IO Clock Net unroutable"


I have added MPMC to my EDK system and added the placement constraints for the DDR pins in my UCF, but when I generate the design, a number of errors occur similar to the following:
"ERROR:Place:901 - IO Clock Net
"DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/delayed_dqs<0>" cannot possibly be routed to component
"DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/dq_ce<0>" (placed in clock region "CLOCKREGION_X0Y2"), since it is too far away from source BUFIO "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_dqs[0].u_iob_dqs/u_bufio_dqs" (placed in clock region "CLOCKREGION_X0Y1").
The situation may be caused by user constraints, or the complexity of thedesign. Constraining the components related to the regional clock properlymay guide the tool to find a solution. To debug your design with partially routed design, please try to allow map/placer to finish the execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1)."

How do I resolve these errors?


This is likely an issue where the MIG constraints have not been applied in your UCF. The problem is with the location of the IODELAY that are connected to the input of the BUFIOs. They are part of the constraints provided by MIG.
To resolve this problem, run through MIG/MPMC tool flow to generate the required MIG constraints and use them in your UCF. More information about the MIG/MPMC tool flow can be found in the MPMC data sheet.
AR# 34297
Date 12/15/2012
Status Active
Type General Article
  • Virtex-5 LXT
  • ISE Design Suite - 11.4
  • Multi-Port Memory Controller (MPMC)
Page Bookmarked