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# AR# 34299

## Description

I saw the DIRECT and DERIVATION columns in the timing data sheet section. What does they mean?

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint| Requirement |-------------+------------- |-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative| Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_n| 2.500ns| 1.850ns| 2.191ns| 0| 0| 0| 39051|
| TS_u_infra_clk_pll | 5.000ns| 4.382ns| N/A| 0| 0| 39051| 0|
| TS_u_infra_clk_mem| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| TS_clk_wr| 2.500ns| N/A| N/A| 0| 0| 0| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

## Solution

The DCM/PLL input clock sys_clk has derived 3 clocks which have different frequencies.

In the TS_u_infra_clk_pll domain, the maximum path delay is 4.382 ns. However, its period requirement is 5 ns, which is twice of the input clock. So, to get a minimum period value at the input, this path delay is divided by two, according to the derivation relationship between the CLKIN and CLKOUT. In this case, 2.191 ns equals (4.382/2) ns.

All the direct path delays inother derived clock domains will be calculated to the input clock domain, and only the worst-case path is listed in this table.

AR# 34299
Date 12/15/2012
Status Active
Type General Article
Tools
• ISE Design Suite - 11.4
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