(Xilinx Answer 34383) - How to create a custom UCF or modify the MIG UCF ensuring all design requirements are followed?
(Xilinx Answer 35085) - How many banks can the Virtex-6 DDR2/DDR3 design span?
(Xilinx Answer 34317) - Usage of Inner Column for Address/Control Group
(Xilinx Answer 34390) - Usage of Inner/Outer Columns for Data Group
(Xilinx Answer 33268) - When using Multiple Controllers, is it possible to share MMCM resources?
(Xilinx Answer 33607) - Is it possible to swap data bytes in the MIG output?
(Xilinx Answer 34477) - Why does the UCF include pin prohibits and LOC constraints for capture (CPT) logic? Can these be moved?
(Xilinx Answer 34540) - Why does the UCF include pin prohibits and LOC constraints for resynchronization (RSYNC) logic? Can these be moved?
(Xilinx Answer 34543) - Do DQS pins need to be allocated on Clock Capable I/O (CCIO) pins?
(Xilinx Answer 34570) - Is it possible to maximize the DDR groups within a bank for a single controller design? Includes information on splitting address/control across banks, removing memory interface signals (ie - DM), using Internal VREF, and DCI Cascade.
(Xilinx Answer 39067)- MIG Virtex-6 DDR2 - I cannot select BUFIO PINs in the dropdown list when creating a DDR2 MIG v3.6 design with AXI interface enabled. Why?