AR# 34322: MIG 7 Series and Virtex-6 DDR2/DDR3 - MIG Options
MIG 7 Series and Virtex-6 DDR2/DDR3 - MIG Options
This section of the MIG Design Assistant focuses on the available MIG options for 7 Series and Virtex-6 DDR3/DDR2 designs. The MIG tool is designed to walk users through generation of a MIG core without needing to refer to additional documentation. If questions do exist on a specific MIG option, please refer to the DDR2 and DDR3 SDRAM Memory Interface Solution > Getting Started with the CORE Generator Tool > Creating Virtex-6 FPGA DDR3 Memory Controller Block Design section within The Virtex-6 FPGA Memory Interfaces User Guide or DDR2 and DDR3 SDRAM Memory Interface Solution > Getting Started with the CORE Generator Tool > Creating 7 Series FPGA DDR3 Memory Controller Block Design section within the 7 Series FPGAs Memory Interface Solutions User Guide.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
For information on the specific features supported by the MIG 7 Series and Virtex-6 DDR3/DDR2 designs, please see:
Customers often have further questions on the pin-out and banking requirements of the core. You can find information on these requirements on the Description Tab of the Bank Selection tab in the MIG tool. For more information, please see: