This section of the MIG Design Assistant focuses on using multi-controller implementations with Virtex-6 DDR3/DDR2/QDRII+ FPGA designs. Below you will find information related to your specific question.
NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
MIG supports DDR3 and QDRII+ multi-controllers through the MIG tool. Up to 8 controllers of either DDR3, QDRII+, or a combination of both can be designed within the tool. During bank selection, the tool recognizes if the number of controllers specified cannot fit in the selected FPGA device. The DDR3 and DDR2 Memory Interface Solution > Getting Started section of The Virtex-6 Memory Interface User Guide discusses generation of multi-controllers.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 34329 | MIG Virtex-6 DDR2 - Multi-Controller Support | N/A | N/A |
| 34282 | MIG Design Assistant - Virtex-6 Core Functionality | N/A | N/A |
| 33268 | MIG Virtex-6 DDR2/DDR3 - Is it possible to combine MMCMs to save MMCM resources in multi-controller designs? | N/A | N/A |
| 34267 | MIG v3.2-3.4 Virtex-6 DDR3 - Can banks be shared between multiple memory controllers? | N/A | N/A |
| 34316 | MIG Virtex-6 DDR2/DDR3 - Supported Features | N/A | N/A |