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AR# 34346

11.4 Virtex-6 Place - "ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component..."


The following error occurs when I use cascaded BUFGs in my Virtex-6 FPGA design:

" ERROR:Place:1131 - Unroutable Placement! A cascaded BUFGCTRL clock component pair have been found that are not placed at a routable site pair. The driver BUFGCTRL component <BUFG_1> is placed at site <BUFGCTRL_X0Y3>. The load BUFGCTRL component <BUFG_2> is placed at site <BUFGCTRL_X0Y1>. The BUFGCTRL components can use the fast path between them if they are placed in adjacent BUFGCTRL sites, and both are in the same half of the device (TOP or BOTTOM). You may want to analyze why this problem exists and correct it. This placement is UNROUTABLE in PAR and therefore, this error condition should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING in order to generate an NCD file. This NCD file can then be used in FPGA Editor to debug the problem. A list of all the COMP.PINS used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to demote this ERROR to a WARNING."

I am familiar with using CLOCK_DEDICATED_ROUTE constraints to downgrade the error to a warning, but it is not clear how to do that in this case. None of the constraints I have tried have worked.


There are three things wrong with this error message:

  1. The placement of BUFGCTRLs into non-adjacent sites is not unroutable as the message states, but is a non-optimal placement since the cascade connection will have more delay that it would if adjacent sites were used. A CLOCK_DEDICATED_ROUTE style error is valid, but the message text should be changed.
  2. Normally a CLOCK_DEDICATED_ROUTE style error message will include the constraints needed to downgrade the error to a warning. This message mentions the constraints but fails to print them.
  3. The CLOCK_DEDICATED_ROUTE constraints that should downgrade the error to a warning do not work.

A CR is under investigation to correct all three issues. These issues can be avoided by constraining the cascaded BUFGCTRLs to adjacent sites in the same half (Top/Bottom) of the device. The top and bottom sites in each set of 16 can be considered to be adjacent to each other since a dedicated routing resource exists between the sites.

It is possible to use the non-optimal placement by using the following environment variable to downgrade the error to a warning:



WARNING: This variable will downgrade all clock checks to warnings. It is important to review all clock warning messages to ensure that all non-optimal placement issues are well understood.

For more general information about setting ISE environment variables, see (Xilinx Answer 11630).

AR# 34346
Date 03/02/2010
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4