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AR# 34354

13.3 Spartan-6 Place - ERROR:Place:1348 - A BUFH, , has been used in this design without placement (LOC) constraints

Description

I have instantiated a BUFH in my design for a small clock netbecause I am already using all of the BUFGCTRLs. During implementation, MAP fails with the following placement error that says I have to LOC the BUFH:

"ERROR:Place:1348 - A BUFH, <XYZ>, has been used in this design without placement (LOC) constraints. In the current version of the implementation tools, manual placement of BUFHs is required in order to properly implement the design. Please add a valid LOC constraint to the UCF file similar to: INST <XYZ> LOC=BUFH_XxYy;

Where the lower case x and y are replaced by the proper coordinates for a BUFH that can be connected to the source and destinations for that buffer. Please refer to the Spartan-6 Clocking Resources User Guide for more details."

Why is this necessary and what are the restrictions for BUFH usage?

Solution

The BUFH is a resource used to access the 16 clock spines in each Spartan-6 FPGA clock region. When a BUFGCTRL is used to drive a clock load in a clock region the Router inserts a "route-thru" to utilize a BUFH site as a resource to reach one of of the clock spines in that clock region. It is also possible for a designer to instantiate a BUFH instance to access a clock spine without using a BUFGCTRL. For each BUFH used this way, one BUFGCTRL will not be able to access the corresponding clock region. The clock placer is currently unable to floorplan a design to compensate for instantiated BUFH components so it is necessary for the designer to constrain the design to prevent conflicts:


  1. Constrain the instantiated BUFH to a site corresponding to the clock region that will be used.
  2. Constrain the BUFH clock loads to that clock region.
  3. Prevent a conflict with the corresponding BUFG site by either:
    • Prohibiting the use of the corresponding BUFG site
    • Range constraining the clock domain for the corresponding BUFG site so that it does not use the clock region used by the BUFH component.

Example:
//Constrain BUFH to site corresponding clock region //
INST"Some_BUFH" LOC=BUFH_X3Y7;


//Constrain BUFH net loads to clock region //
NET "Some_BUFH_Net" TNM_NET = "TN_Some_BUFH_Net" ;
TIMEGRP "TN_Some_BUFH_Net" AREA_GROUP = "CLKAG_Some_BUFH_Net" ;
AREA_GROUP "CLKAG_Some_BUFH_Net" RANGE = CLOCKREGION_X1Y0;



//Constrain BUFGCTRL net away from clock region //

NET "Some_BUFG_Net" TNM_NET = "TN_Some_BUFG_Net" ;
TIMEGRP "TN_Some_BUFG_Net" AREA_GROUP = "CLKAG_Some_BUFG_Net" ;
AREA_GROUP "CLKAG_Some_BUFH_Net" RANGE =CLOCKREGION_X0Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7, CLOCKREGION_X0Y8, CLOCKREGION_X1Y8, CLOCKREGION_X0Y9, CLOCKREGION_X1Y9, CLOCKREGION_X0Y10, CLOCKREGION_X1Y10, CLOCKREGION_X0Y11, CLOCKREGION_X1Y11 ;



This image is an FPGA Editor view of the BUFH sites used to access one clock region. The blue site is an instantiated BUFH component and there are four BUFGCTRL nets using route-thrus to access the clock region.

AR# 34354
Date Created 02/09/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
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  • ISE Design Suite - 13.1
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