This section of the MIG Design Assistant focuses on the Multi-Purpose Register defined by the JEDEC Spec, as it applies to the MIG Virtex-6 and 7 Series DDR3 designs.
NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or trouble shooting a problem, use the MIG Solution Center to guide you to the right information.
The Multi-Purpose Register is a new feature in DDR3 Memories and is defined in section 4.10 of JEDEC specification JESD79-3 DDR3 SDRAM Standard.
MIG Virtex-6 MPR Usage
Reads from the Multi-Purpose Register can be used for read calibration however the Multi-Purpose Register is not used by the Virtex-6 MIG DDR3 memory controller. For details on how read leveling is performed by the MIG Controller refer to UG406, Chapter 1 DDR2 and DDR3 SDRAM Memory Interface Solution > Core Architecture > PHY and (Xilinx Answer 35118).
MIG 7 Series MPR Usage
Reads from the Multi-Purpose Register are used in the MIG 7 Series DDR3 calibration process. The MPR Read Leveling stage is performed immediately after Write Leveling. At this stage of calibration, the write DQS is not centered in the write DQ window and the read DQS is not centered in the read DQ window. The DDR3 Multi-Purpose Register (MPR) is used to center the read DQS in the read DQ window using the MPR pre-defined 01010101 or 10101010 pattern. This intermediate read leveling stage is required before the next stage of calibration, OCLKDELAYED calibration, is completed. Please see UG586 > DDR3 and DDR2 Memory Interface Solutions > Core Architecture > PHY and (Xilinx Answer 51954) for more information. For information on debugging MPR Read Leveling Failures, please see (Xilinx Answer 43879).