AR# 34380: LogiCORE IP Video On Screen Display (OSD) v1.0 - What is the clk_core port?
LogiCORE IP Video On Screen Display (OSD) v1.0 - What is the clk_core port?
What is the clk_core port?
The clk_core port is the clock that runs the internal clock for the Video On Screen Display IP. It should be connected to a clock that is 2 or 3 times as fast as the video clock which is driving the clk port.
The required clock speed is set by the number of data channels you select when configuring the core. The number of data channels is determined by the number of color planes per layer (i.e. 4:2:2 contains 2 channels, 4:4:4 video contains 3 channels). See Table 1 of the Video On Screen Display v1.0 data sheet for more information on the number of channels selection in the core GUI.
The valid range for channels in the Video On Screen Display v1.0 is 2-3 channels.
clk_core = clk * NUMBER_OF_CHANNELS
For a detailed list of LogiCORE IP Video On Screen Display Release Notes and Known Issues, see (Xilinx Answer 33257).