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AR# 34383

Virtex-6 DDR2/DDR3 - How to create a custom UCF or modify the MIG UCF ensuring all design requirements are followed?

Description

Starting with the MIG 3.4 (ISE tools 12.1) release, the MIG tool includes both a Verify UCF and Update Design and UCF tool and a Fixed Pin Out tool which ensure design requirements are followed. Verify UCF and Update Design and UCF can be used to verify any UCF changes and create an updated design following the UCF locations specified. This tool will also update a MIG design to the newest version. The Fixed Pin Out tool allows on the first generation of a MIG design the ability to enter a pre-existing pin out. The tool then verifies the pin out follows the design requirements and generates the appropriate MIG design.

Prior to MIG 3.4, the only supported UCF changes were:

  • The address and control pin assignments can be swapped with each other as needed.
  • DQ and DM pin assignments within the same byte can be swapped with each other. The affected bits require a change to the pin assignment LOC constraints in the UCF.

For information on Pin Out and Banking Requirements, please see (Xilinx Answer 34308).

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

For information on these features added in MIG 3.4 (ISE 12.1) be see:

(Xilinx Answer 34386) Verify UCF and Update Design and UCF Feature

(Xilinx Answer 34388) Fixed Pin Out Feature

Linked Answer Records

Associated Answer Records

AR# 34383
Date Created 05/19/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG