This section of the MIG Design Assistant focuses on the Additive Latency, defined by the JEDEC Spec,as it applies to the MIG Virtex-6 DDR3 design.NOTE: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
Additive Latency is an efficiency feature in SDRAM memories.It is discussed in section 184.108.40.206 of JEDEC Specification JESD79-3 DDR3 SDRAM Standard and 2.5 of JEDEC Specification JESD79-2 DDR2 SDRAM Standard (in the "Bank activate command" section).Additive latency allows a read or write command to be issued immediately following the active command.
This feature is not supported in the MIG Virtex-6 DDR controller and PHY.Because command reordering is supported, it is unnecessary to support Additive Latency. For more information on controller efficiency and how reordering is used in the Virtex-6 DDR3 design, see (Xilinx Answer 34392).