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  3. AR# 3440: Map M1.4.12 ERROR:basut:162 - This Xilinx application has run out of memory
  4. AR# 34404: SP605 Schematics - PCI Express Endpoint Connectivity section shows clock net name PCIE_250M_N. Should this really be PCIE_125M_N?

AR# 34404

SP605 Schematics - PCI Express Endpoint Connectivity section shows clock net name PCIE_250M_N. Should this really be PCIE_125M_N?

Description

The SP605 schematics (xtp067) show a device ics874001 on Pg. 28 with a differential clock output with the following names:

PCIE_250M_N
PCIE_250M_P

Does this mean that the PCIe clock on the SP605 can run at 250 MHz?

Solution

The SP605 Schematics indicate that settings are such that F_SEL1 = 0 and F_SEL0 = 1, which defines oscillator output is 125 MHz clock. The data sheet for this part (http://www.xilinx.com/products/boards/ml510/datasheets/ics874001.pdf) indicates the same. The net name is a misnomer, 250 MHz is not an option, but the functionality is still as expected by the reference designs shipped with the kit.

This article is to confirm that PCIE_250M_N / PCIE_250M_P pair supports 125 MHz on the SP605.
AR# 34404
Date 04/21/2011
Status Active
Type General Article