UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34407

Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Correct GTX settings for Transceiver Termination

Description

When generating Virtex-6 FPGA Integrated Block Wrapper for PCI Express,the following transceiver parameters are set in the GTX wrapper.

.TERMINATION_CTRL(5'b10101),
.TERMINATION_OVRD("TRUE"),

Are these the correct values?

Solution

The following transceiver parameters are required for ES silicon:

.TERMINATION_CTRL(5'b10101),
.TERMINATION_OVRD("TRUE"),

For production silicon these values should be modified in the file /source/gtx_wrapper_v6.v as follows:

.TERMINATION_CTRL(5'b00000),
.TERMINATION_OVRD("FALSE"),

This will be fixed in the v1.5 release included in ISE software 12.1.

Revision History

03/23/2010 - Initial Release

AR# 34407
Date Created 03/23/2010
Last Updated 05/19/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 LXT
Tools
  • ISE Design Suite - 11.4
IP
  • Endpoint Block Wrapper for PCI Express