Most downstream devices advertise infinite completion credits instead of finite completion creditsso this issue is usually not seen. Even if the link partner does advertise data limited completion credits in some cases the problem can be avoided.
Use the following equation to determine if your design is subject to this condition. If this equation evaluates to TRUE then the condition is hit and your design is subject to a potential transmit stall.
Initial CPLD credits < Initial CPLH * 8 * 2X, where X depends on the MPS value as follows:
| MPS | X |
| 128 | 0 |
| 256 | 1 |
| 512 | 2 |
For example, if the link partner advertises initial CPLH credits as 22 and the initial CPLD credits as 128, for an MPS of 128 then:
128 < 22 * 8 * 1
128 < 176
In this example, the equation evaluates to TRUE and the restriction is hit.
Users should consult the link partner's data sheet for information on initial credit advertisement. Most link partners advertise infinite completion data credits.
This issue has been fixed in the v1.14 release first available in ISE 12.1 design tools. Users must determine if they are interfacing with a completion data credit limited device and if so follow the guidelines documented for this issue in the "Known Restrictions" chapter of the LogiCORE IP Endpoint Block Plus for PCI Express User Guide (UG341). Look for the issue titled: "Link partner initial advertisement of Data Limited CompletionCredits" (page 136 of the user guide dated April 19, 2010). It states: "Users can work around this limitation by restricting Downstream Reads to 1or 2 DW, which must becompleted with exactly one completion." If the link partner is not data credit limited, there are no restrictions to follow.
The LogiCORE IP Endpoint Block Plus for PCI Express User Guide (UG341) is found at:
http://www.xilinx.com/support/documentation/ip_documentation/pcie_blk_plus_ug341.pdf
NOTE: Due to known interoperation issues, Xilinx strongly recommends that customers do not interface Virtex-5 Endpoint Block Plus with components that have Root or Downstream Ports that advertise non-infinite Completion Header or Data credits. Customers can typically find this information in the connected component data sheets or by contacting the connected component vendor.
Revision History
07/05/2011 - Updated title
09/07/2010 - Added information on fix.
02/25/2010 - Initial Release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 33580 | Design Advisory for the Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express Master Answer Record | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 34711 | 11.4 EDK - plbv46_pcie_v4_03_a stalls after warm reset | N/A | N/A |
| 33580 | Design Advisory for the Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express Master Answer Record | N/A | N/A |