AR# 34476


MIG Virtex-6 DDR2/DDR3 - Periodic Reads Disabled for DDR2 200MHz and Below


This section of the MIG Design Assistant focuses on Periodic Reads being disabled for Virtex-6 DDR2 designs running at 200 MHz and below. Below you will find information related to your specific question.

NOTE: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


To correct for voltage and temperature drift over time, the phase detector dynamically locks the phase of the internally generated capture clocks such that they are 90 degrees offset from the DQS[0] signal. The circuit monitors the phase on only DQS[0] as the VT affect on all DQS signals will be nearly identical. As the phase moves, the phase of the capture clocks are adjusted using the phase shift of the MMCM.

For DDR2 designs running at 200 MHz or slower the Phase Detector and the Periodic Reads are turned off because there is a large enough margin where voltage and temperature drifts don't affect results. Disabling of the Period Reads will also improve throughput if your application requires long periods of Writes.

For a detailed description on the Phase Detector Logic please refer to "DDR2 and DDR3 SDRAM Memory Interface Solution"=>"Core Architecture"=>"PHY" section in UG406:

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34480 MIG Virtex-6 DDR2/DDR3 - Phase Detection Circuit and Periodic Reads N/A N/A
34282 MIG Design Assistant - Virtex-6 Core Functionality N/A N/A
AR# 34476
Date 12/15/2012
Status Active
Type General Article
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