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AR# 34490

Serial RapidIO v5.4 - Port_initialized intermittently toggles


There is a potential issue with v5.4 of the core and earlier which can cause port_initialized to occasionally toggle indefinitely. This isbecause ofthe Serial RapidIO core failing to wait until the reset done output of the GT has asserted. Because of this, it is possible that the core will initialize and assert port_initialized prior to the RX Buffer of the GT being cleared, which will result in the link going back down and restarting initialization. This can happen intermittently because of timing on the link, and can occur on power-up or during in-band resets.

This issue is scheduled to be fixed in v5.5 of the core.


To work around this issue, simply modify the srio_gt_wrapper_<version>.v(hd) file to "OR" rxresetdone with RXDISPERR. For example, change the following based on your lane width and HDL language:

1x Verilog:
assign RXDISPERR0[0] = RXDISPERR0_swap[1] || ~rxresetdone;
assign RXDISPERR0[1] = RXDISPERR0_swap[0] || ~rxresetdone;

4x Verilog:
assign RXDISPERR0[0] = RXDISPERR0_swap[1] || ~rxresetdone0;
assign RXDISPERR0[1] = RXDISPERR0_swap[0] || ~rxresetdone0;
assign RXDISPERR1[0] = RXDISPERR1_swap[1] || ~rxresetdone1;
assign RXDISPERR1[1] = RXDISPERR1_swap[0] || ~rxresetdone1;
assign RXDISPERR2[0] = RXDISPERR2_swap[1] || ~rxresetdone2;
assign RXDISPERR2[1] = RXDISPERR2_swap[0] || ~rxresetdone2;
assign RXDISPERR3[0] = RXDISPERR3_swap[1] || ~rxresetdone3;
assign RXDISPERR3[1] = RXDISPERR3_swap[0] || ~rxresetdone3;

1x VHDL:
RXDISPERR0(0) <= RXDISPERR0_swap(1) or not(rxresetdone);
RXDISPERR0(1) <= RXDISPERR0_swap(0) or not(rxresetdone);

4x VHDL:
RXDISPERR0(0) <= RXDISPERR0_swap(1) or not(rxresetdone0);
RXDISPERR0(1) <= RXDISPERR0_swap(0) or not(rxresetdone0);
RXDISPERR1(0) <= RXDISPERR1_swap(1) or not(rxresetdone1);
RXDISPERR1(1) <= RXDISPERR1_swap(0) or not(rxresetdone1);
RXDISPERR2(0) <= RXDISPERR2_swap(1) or not(rxresetdone2);
RXDISPERR2(1) <= RXDISPERR2_swap(0) or not(rxresetdone2);
RXDISPERR3(0) <= RXDISPERR3_swap(1) or not(rxresetdone3);
RXDISPERR3(1) <= RXDISPERR3_swap(0) or not(rxresetdone3);

AR# 34490
Date 12/15/2012
Status Active
Type General Article
  • Virtex-4 FX
  • Virtex-5 FXT
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • Serial RapidIO