UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34539

Virtex-6 FPGA GTX Transceiver Wizard v1.4 - "Error: Integer literal 1 is not of type ieee.std_logic_1164.std_logic"

Description

The following error occurs when I synthesize the VHDL outputs from the Virtex-6 FPGA GTX Transceiver Wizard:

"Error: ../../example_design/rx_sync.vhd(231): Integer literal 1 is not of type ieee.std_logic_1164.std_logic"

This Answer Record discusses the changes that need to be made to the code to work around this problem.

Solution

The VHDL code mistakenly uses Verilog constant definitions. Changing the following assignments in the rx_sync.vhd module bypasses this error:

RXDLYALIGNRESET <= 1'b0; and RXDLYALIGNDISABLE <= 1'b0;

to:

RXDLYALIGNRESET <= '0'; and RXDLYALIGNDISABLE <= '0';

AR# 34539
Date Created 03/01/2010
Last Updated 03/10/2010
Status Active
Type Known Issues
Devices
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6 HXT
IP
  • Virtex-6 GTX Transceiver Wizard