DQS does not need to be LOCed to a CCIO site in the Virtex-6 design. It only needs to be LOCed to a p/n General Purpose I/O (GPIO) pair. The internally generated clocks (CPT and RSYNC) instead use clocking resources, and therefore require CCIO.
To view the PHY clocking structure for the Virtex-6 DDR2/DDR3 MIG design, see the PHY Clocking Architecture Figure in theVirtex-6 FPGA Memory Interface Solutions User Guide (UG406): http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf
For more information on the Design/Layout Guidelines for this design, please see: