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AR# 34548

11.4 Route-WARNING:Route:436 - The router has detected an unroutable situation for the CLKPERF pin of OSERDES


I encountered the following warning in PAR.

It states that the clock net (ddr_clk_wr_i) from a BUFG cannot be routed to the CLKPERF pin of an OSERDES component.

WARNING:Route:436 - The router has detected an unroutable situation for one or more connections.
The router will finish the rest of the design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints.
   To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:
  Unroutable   signal: ddr_clk_wr_i   pin:
  Unroutable   signal: ddr_clk_wr_i   pin:
  Unroutable   signal: ddr_clk_wr_i   pin:
  Unroutable   signal: ddr_clk_wr_i   pin:

How can I solve this problem?


In Virtex-6 devices, there is a dedicated high performance path for a clock net from MMCM to the CLKPERF pin of OSERDES.

This clock net should be connected from the MMCM output port to the CLKPERF pin of OSERDES directly without going through a BUFG.

Removing the BUFG from the clock net resolves this problem.
AR# 34548
Date 07/31/2014
Status Active
Type Error Message
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • ISE Design Suite - 11.4