UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34562

SPI-4.2 Lite v5.1 Rev2 - MMCM Mult values outside of allowable range in Virtex-6 FPGA

Description

The SPI-4.2 Lite core's clocking example designs for Virtex-6 FPGA use incorrect values for the MMCM attributes "DIVCLK_DIVIDE" and "CLKFBOUT_MULT_F" that might cause the MMCMs to operate outside of the supported range.

Solution

1) Sink Clock example design (pl4_lite_snk_clk.v/vhd)

For the "mmcm0" instance of MMCM (connects to RDClk clock):

Add the "DIVCLK_DIVIDE" parameter with a value of 4.
Change the value of "CLKFBOUT_MULT_F" to 8.0.

All other parameters are correct.

2) Source Clock example design (pl4_lite_src_clk.v/vhd)

For the "mmcm0" instance of MMCM (connects to SysClk clock):

Add the "DIVCLK_DIVIDE" parameter with a value of 4.
Change the value of "CLKFBOUT_MULT_F" to 8.0.

All other parameters are correct.

This issue is fixed in v5.2 of the core (available in ISE Design Suite 12.1).

AR# 34562
Date Created 03/03/2010
Last Updated 05/23/2014
Status Archive
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • SPI-4 Phase 2 Interface Solutions