Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.
This Design Advisory covers the Virtex-6 FPGA and related issues that impact Virtex-6 FPGA designs.
Design Advisories Alerted on March 8th, 2021
| 04/07/2021 | (Xilinx Answer 76171) | Design Advisory: Xilinx recommends that the user generates their own keys for fielded systems and then provide those keys to the development tools. | [SECURITY] |
Design Advisories Alerted on April 20th, 2020
| 04/15/2020 | (Xilinx Answer 73541) | Design Advisory for 7 Series/Virtex-6 FPGAs: Defeating Bitstream Encryption. | [SECURITY] |
Design Advisory Alerted on April 8, 2013:
| 04/05/2013 | (Xilinx Answer 45166) | Updated Design Advisory for Virtex-6 FPGA GTH Transceiver to include the updated RX_P1_CTRL attribute value |
Design Advisory Alerted on August 13, 2012:
| 08/15/2012 | (Xilinx Answer 51145) | Design Advisory14.2 iMPACT - Indirect Programming on Virtex-6 causes tool to crash without warning |
Design Advisory Alerted on May 21, 2012:
| 05/17/2012 | (Xilinx Answer 47938) | Design Advisory for Virtex-6 FPGA Designs using OPAD Tioop/Tiotp must be re-run through timing analysis |
Design Advisory Alerted on February 13, 2012:
| 01/25/2012 | Update to (Xilinx Answer 42444) | Design Advisory for Virtex-6 FPGA Designs using 18K/36K block RAM or 18K/36K FIFO must be re-run through timing analysis |
Design Advisory Alerted on January 16, 2012:
| 01/13/2012 | (Xilinx Answer 45166) | Design Advisory for Virtex-6 GTH Transceiver on burst of errors at startup and RXRECCLK not toggling at startup |
Design Advisory Alerted on December 19, 2011:
| 12/13/2011 | (Xilinx Answer 43591) | Updated Design Advisory for Virtex-6 FPGA GTH Transceivers on RXBUFRESET-related initialization sequence and BUFFER_CONFIG_LANEx issues to include fix information for ES Silicon |
Design Advisory Alerted on November 21, 2011:
| 11/21/2011 | (Xilinx Answer 44174) | Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup |
Design Advisories Alerted on September 19, 2011:
| 09/19/2011 | (Xilinx Answer 43829) | Design Advisory for Virtex-6 FPGA GTH Transceivers -Incorrect RXBUFRESET connections in the wrapper in x4 Mode |
Design Advisories Alerted on August 22, 2011:
| 08/22/2011 | (Xilinx Answer 43591) | Design Advisory for Virtex-6 FPGA GTH Transceivers Updates required to address RXBUFRESET-related initialization sequence and BUFFER_CONFIG_LANE -x issues |
Design Advisories Alerted on August 8, 2011:
| 08/08/2011 | (Xilinx Answer 43346) | Design Advisory for Virtex-6 GTH Recommendation for Non-retimed 10G+ Optical Interfaces (e.g., SFP+ and QSFP) |
| 08/08/2011 | (Xilinx Answer 42682) | Design Advisory for Virtex-6 FPGA13.x iMPACT eFUSE key programming incorrect when target FPGA is not the only device in the JTAG chain |
Design Advisories Alerted on July 11, 2011:
| 07/08/2011 | (Xilinx Answer 42444) | Design Advisory for Virtex-6 FPGA Designs using 18K/36K block RAM or 18K/36K FIFO must be re-run through timing analysis |
| 07/07/2011 | (Xilinx Answer 41821) | Design Advisory for Virtex-6 FPGA BitGen Option -g Next_Config_Addr: Default Value Changed |
| 07/07/2011 | (Xilinx Answer 41099) | Design Advisory for Virtex-6 FPGA Synchronous FIFOs must have reset synchronized to RDCLK/WRCLK |
Design Advisories Alerted on July 6, 2011:
| 07/01/2011 | (Xilinx Answer 42444) | Design Advisory for Virtex-6 FPGA Designs using 18K/36K block RAM or 18K FIFO must be re-run through timing analysis |
| 06/30/2011 | (Xilinx Answer 42682) | Design Advisory for Virtex-6 FPGA13.x iMPACT eFUSE key programming incorrect when target FPGA is not the only device in the JTAG chain |
| 04/11/2011 | (Xilinx Answer 41099) | Design Advisory for Virtex-6 FPGA Synchronous FIFOs must have reset synchronized to RDCLK/WRCLK |
Design Advisories Alerted on March 21, 2011:
| 03/18/2011 | (Xilinx Answer 40885) | Updated Design Advisory for Virtex-6 FPGA Production GTH Transceivers to include GTH TXUSERCLKOUT/RXUSERCLKOUT operational guideline. |
Design Advisories Alerted on March 7, 2011:
| 03/04/2011 | (Xilinx Answer 40885) | Design Advisory for Virtex-6 FPGA Production GTH Transceivers |
Design Advisories Alerted on October 18, 2010:
| 10/11/2010 | (Xilinx Answer 38132) | Virtex-6 FPGA MMCM Design Advisory MMCM BANDWIDTH attribute requirement |
| 10/11/2010 | (Xilinx Answer 38133) | Virtex-6 FPGA MMCM Design Advisory Restriction for DIVCLK_DIVIDE value when Fclkin > 315 MHz |
| 09/27/2010 | (Xilinx Answer 38134) | Virtex-6 Configuration PROGRAM_B pin held Low prior to power up does not delay configuration |
| 09/07/2010 | (Xilinx Answer 36642) | Virtex-6 System Monitor Maximum DCLK frequency revised down to 80 MHz |
Design Advisories Alerted on August 30, 2010:
| 08/27/2010 | (Xilinx Answer 37667) | Virtex-6 FPGA -1L Industrial Grade Vccint Specification Change |
Design Advisories Alerted on March 22, 2010:
| 03/19/2010 | (Xilinx Answer 34859) | Virtex-6 FPGA Block RAM Design Advisory Address Space Overlap |
| 02/11/2010 | (Xilinx Answer 33849) | Virtex-6 FPGA MMCM New Requirements for all MMCMs, VCO minimum frequency, and CLKBOUT_MULT_F values |
| 01/22/2010 | (Xilinx Answer 34164) | Virtex-6 11.4 ISE - Virtex-6 FPGA designs must be re-run through implementation in ISE 11.5 or later software |
Revision History:
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 34963 | Xilinx Virtex-6 FPGA Solution Center | N/A | N/A |
| 40687 | Packaging Solution Center | N/A | N/A |