Note: Not recommended for new designs. The core is removed from IP catalog as of 2014.1. Please contact Xylon, our IP partner, for solutions related to image characterization.
(Xilinx Answer 35641) Why is the control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6 FPGA?
Known Issues
(Xilinx Answer 38527) Why is the Image Characterization so large when using the pCore interface?
(Xilinx Answer 38529) Why does the pCore fail to synthesize in EDK, with an error on the user_logic.vhd file?
LogiCORE IP Image Characterization v1.0
Initial release in ISE Design Suite 12.1
New Features
Programmable register control
Selectable processor interface
EDK pCore
General Purpose Processor
Global and Block Means and Variances for:
Luminance / Chrominance Content
Edge Content
Motion Content
Color Content
Global Histograms for:
Luminance
Chrominance
Hue
Support for 8-bit, YUV 4:2:2 or YUV 4:2:0 data
Support for 8-bit Motion data
Support for image sizes up to 1920x1080p @30fps or 1280x720 @ 60fps
Support for Virtex-6, Spartan-6, Virtex-5 and Spartan-3A DSP FPGAs
ISE 12.1 software support
Programmable register control
Bug Fixes
N/A
Known Issues
(Xilinx Answer 35641) Why is the control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6 FPGA?