Once the board layout is verified, the next step in hardware debug is to load the provided MIG Example Design with the Debug Port enabled on the board.
The Debug Port includes critical debug signals brought up through ChipScope modules that are used in this debug flow.
To enable the Debug Port, generate your MIG design and Enable the Debug Signals for Memory Controller on the FPGA Options GUI screen.
For more information on the debug port, see (Xilinx Answer 35206).
The Example Design is a known working design with a fully operational Traffic Generator.
The Traffic Generator sends out write commands, reads back the data, and performs a comparison to ensure a working system.
The Traffic Generator can be configured to send many different types of data patterns to test for different board related issues such as SSO and Cross-Talk.
For information on the Traffic Generator and its patterns, please see the DDR2/DDR3 SDRAM Memory Interface Solution > Getting Started section of (UG406).
Once the Example Design is running in your hardware, there are a few simple checks to determine the high level failure occurring.
Monitor the phy_init_done and error flags to determine if a calibration or bit/data error has occurred:
Are the clocks toggling?
- Check is the MMCM locked (pll_lock in infrastructure.v)
- Check if IODELAY Control Ready goes high (iodelay_ctrl_rdy in example_top.v)
- Verify input PCB clock sources and output CK/CK# using oscilloscope
Check the reset polarity of the design
- Check the RST_ACT_LOW parameter value is correct
Debugging Calibration Failures - (Xilinx Answer 34743)
Debugging Data Errors - (Xilinx Answer 34709)