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AR# 34620

11.x ISE Simulator (ISim) - WARNING:HDLCompiler:89 - "my_module" remains a black-box since it has no binding entity

Description

I have a design that synthesizes successfully in ISE.

All HDL describing my modules are accounted for (there are no question marks in the ISE Hierarchy viewer). 

However, when I attempt to simulate in ISim, I encounter the following warning:

Starting static elaboration
WARNING:HDLCompiler:89 - "/designs/my_testbench.vhd" Line 174: <my_uut> remains a black-box since it has no binding entity.

In the ISim GUI, I only see signals declared at the testbench level. 

The rest of my design appears to be missing.

What could be causing this problem and how can I address it?

Solution

The warning indicates that the ISim compiler (fuse) has not compiled HDL that describes the entity in question. 

This can occur if the HDL for the design has been compiled into a library other than "work" but no LIBRARY/USE clauses have been added in the RTL to point to it.

Please make sure that entities compiled into libraries other than work are being referenced via LIBRARY/USE clauses. 

For example, if your design compiles RTL to a library called "fpga_rtl", while your testbench is compiled into "work", then the following lines should be added to the top of the testbench RTL:

Library fpga_rtl;
Use fpga_rtl.all;


Alternatively you can use direct instantiation to point to the appropriate library during instantiation of the entity:

uut: fpga_rtl.my_uut 
PORT MAP(
...
);


AR# 34620
Date Created 03/07/2010
Last Updated 09/11/2014
Status Active
Type General Article
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4