We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34629

SPI-4.2 - Spartan-6 FPGA example design might fail timing on RStat pins


When implementing the SPI-4.2 example design for Spartan-6 devices, the design might fail to meet timing due to MAP placing the Rstat_N_P<0> and Rstat_N_P<1> pins on opposite sides of the device. The timing failure looks similar to the following:

Example timing failure

Timing constraint: TS_pl4_snk_clk0_clk_div = PERIOD TIMEGRP
"pl4_snk_clk0_clk_div" TS_RDClk_P / 2 HIGH 50% INPUT_JITTER 0.3 ns;

5882 paths analyzed, 3637 endpoints analyzed, 2 failing endpoints
2 timing errors detected. (2 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 6.178ns.
Slack: -0.464ns (requirement - (data path - clock path skew + uncertainty))
Source: core_pl4_snk_top0/U0/c1.cal0/RStat_d3_1 (FF)
Destination: core_pl4_snk_top0/U0/c1.cal0/rstat1_ff (FF)
Requirement: 5.714ns
Data Path Delay: 6.420ns (Levels of Logic = 0)
Clock Path Skew: 0.396ns (1.134 - 0.738)
Source Clock: RDClkDiv_User rising at 0.000ns
Destination Clock: RDClkDiv_User rising at 5.714ns
Clock Uncertainty: 0.154ns

Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.300ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns

Maximum Data Path at Slow Process Corner: core_pl4_snk_top0/U0/c1.cal0/RStat_d3_1 to core_pl4_snk_top0/U0/c1.cal0/rstat1_ff
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X11Y62.DQ Tcko 0.430 core_pl4_snk_top0/U0/c1.cal0/RStat_d3<1>
OLOGIC_X16Y1.D1 net (fanout=1) 5.220 core_pl4_snk_top0/U0/c1.cal0/RStat_d3<1>
OLOGIC_X16Y1.CLK0 Todck 0.770 RStat_i(1)
------------------------------------------------- ---------------------------
Total 6.420ns (1.200ns logic, 5.220ns route)
(18.7% logic, 81.3% route)


To work around this issue, place LOC constraints on the RSTAT pins to lock them down to a location on the same side of the device.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
35109 SPI-4.2 v10.1 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

Associated Answer Records

AR# 34629
Date 12/15/2012
Status Active
Type General Article
  • ISE Design Suite - 12.1
  • SPI-4 Phase 2 Interface Solutions