The IDDR2 and ODDR2 registers in a Spartan-6 FPGA have two clock inputs, C0 and C1.They are both supposed to capture on the rising edge.
Normal DDR behavior is emulated by taking the same clock that goes to C0, inverting it with a BUFIO2, and then sending that clock to C1.
The problem is that in my Timing Analyzer report (TWR), I see the analysis done on the rising edge and at the first clock edge for both the rising and falling analysis.
My separate constraint with the FALLING keyword shows zero items analyzed:
The RISING and FALLING Keywords are still working as expected, but might not work for IDDR2 and ODDR2 primitives as expected.
The RISING and FALLING keywords are grouping filters that limit components to 'clocked on rising edge' and 'clocked on falling edge'.
Because both C0 and C1 are clocking on rising edges when the local inverter is not used in IDDR2 and ODDR2, the FALLING Keyword does not apply.
To help make the timing reports clearer, we will be adding a 180 degree phase shift to BUFIO2 inverted clocks so that the arrival times will correctly represent the clock edges when the analysis is done.
However, even after this change, the FALLING keyword will still not be applicable.
To work around this issue, use Solution 2 of (Xilinx Answer 12819), or use the following example:
1. This is also applicable when the 180 degree phase shift of C1 is done by PLL/DCM for IDDR2 or ODDR2.
2. If the local inverter is used on the C0 or C1 pins, both RISING and FALLING keyword work as expected.