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AR# 34652

Virtex-6 FPGA Connectivity Kit TRD - TRD Uses Custom MIG Files

Description

Why does the TRD notuse the MIG straight out of the CORE Generator interface?

Why do I need modified files?

What happens when the MIG version changes and I need to update?

Solution

The TRD uses the Native Interface layer instead ofUser Interface layer because it supports a request tagging feature which is useful to identify which port the data belongs to - required for Multiport functionality. The Request Tagging feature can also be implemented around the User Interface layer, but this only increase the design size and latency.

The modified file mc.v was necessary to meet timing on a critical path. This modification will be available from MIG version 3.4 onwards.

The file infrastructure.v has been modified to bring out the pll_lock signal as an output. This signal is being used as a reset in the TRD.

When MIG updates in the CORE Generator software, there might be some port changes at the Native Interface level. The TRD is to be updated for all the major release starting with ISE 12.1 software, so you can wait for the new release to get the new MIG version integrated into the TRD.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34432 Virtex-6 FPGA Connectivity Kit and Targeted Reference Design (TRD) - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34432 Virtex-6 FPGA Connectivity Kit and Targeted Reference Design (TRD) - Release Notes and Known Issues N/A N/A
AR# 34652
Date Created 04/09/2010
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • MIG
Boards & Kits
  • Virtex-6 FPGA Connectivity Kit