AR# 34669: ChipScope, Analyzer IBERT - "ERROR:XSDB Master could not reset the System Clock. The System Clock is not locked. The System Clock is not running"
ChipScope, Analyzer IBERT - "ERROR:XSDB Master could not reset the System Clock. The System Clock is not locked. The System Clock is not running"
WhenI connect to my IBERT core using the ChipScope analyzer, the following error occurs:
"ERROR:XSDB Master could not reset the System Clock. The System Clock is not locked. The System Clock is not running"
"ERROR: XSDB Master timed out."
How doI work around this issue?
This error is caused by either a missing input system clock or a PLL that has been incorrectly reset. If the system clock was obtained from a GT, then a reset or line rate change to the GT could cause the system clock to momentarily disappear. Disconnecting and reconnecting to the cable can cause this on ChipScope tool 11.x.
If you are using an external (off chip) clock for the system clock, then it is most likely a noise issue. The LL can lose lock; this happens when the clock is lost (as already mentioned), or if there is some noise on the power supply whereby the LL is unable to keep the VCCO frequency running at the proper rate.
In all these cases, the result of receiving this erroristo attempt to reset the PLL and see if a lock is obtained. If this does not help, look for the following possible causes:
The system clock is locked to an incorrect pin location. To work around this issue, regenerate the core while taking care to specify the correct pin.
A badly terminated clock or noisy clock is used as System Clock. This might require on-board termination, or alternatively (for IBERT 11.x), using an LVDS clock may exhibit this as DIFF_TERM is not enabled. See (Xilinx Answer 35420).
Virtex-6 FPGA IBERT GTX uses TXOUTCLK as system clock. The core is affected by the issue described in (Xilinx Answer 35681). To work around this issue use the TXOUTCLK from a different GT as a system clock or alternately use an external clock as system clock.