We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34675

Spartan-6 -1L - Lower Power Devices use an additional low power reset circuit for DCM_SP and DCM_CLKGEN


Spartan-6 Lower Power devices require an additional reset circuit to ensure proper operation of the DFS outputs for both DCM_SP (CLKFX and CLKFX180 outputs) and DCM_CLKGEN. Designs that do not have the correct reset circuitry are not guaranteed to have the correct output frequency. The device will not be damaged.

The Low Power Reset Circuit is not inserted in ISE Design Suite 11.5. Designs using DCM_SP with the DFS outputs or DCM_CLKGEN will not generate a programming file in ISE Design Suite 11.5, see (Xilinx Answer 34102).

The circuit is inserted beginning in ISE Design Suite 12.1.


In ISE Design Suite 12.1, a low power reset circuit is automatically inferred in any design using the DFS outputs of DCM_SP or DCM_CLKGEN. The low power reset circuit monitors the behavior of the reserved status ports for STATUS[5] and STATUS[7] to determine if a reset is required. The low power reset circuit requires the addition of seven SLICEs for the reset circuitry. The reset circuit requires four Shift Registers, five Slice Registers, and nine Slice LUTs.

Figure 1:

For design entry, DCM_CLKGEN continues to support STATUS[2:1].ISE software and the simulation models show STATUS[7:0] for DCM_CLKGEN because STATUS[5] and STATUS[7] are required for the low power reset circuit.

The low-power reset circuitry is automatically inserted during the MAP phase. As a result, XST and TRANSLATE do not show the low power reset circuit. Post-Synthesis simulations and Post-Translate simulations similarly do not reflect the low power circuit.

Table 1: ISE Software Tools Inclusion of DCM Low-Power Reset Circuit
XST Translate Map PAR
Low-Power Reset Circuit No No Yes Yes
STATUS (DCM_CLKGEN) [2:1] [7:0] [7:0] [7:0]
STATUS (DCM_SP) [7:0] [7:0] [7:0] [7:0]

The low power circuit has been designed to support the full frequency ranges of DCM_SP and DCM_CLKGEN. No other design changes are required.

While not advised, the automatic insertion of the reset circuitry can be disabled adding the following design property to a UCF:

inst "< inst_name >" INSERT_LP_DFS_RESET_CIRCUIT = FALSE;

Workaround for Earlier SW Versions- For effected designs in 11.4 or 11.5, the following options are possible work-arounds:
Please use the DCM_SP using only the DLL functionality or PLL_BASE as an alternative.

For example, high speed DDR interfaces (IDDR2/ODDR2) requiring clock multiplication may still be able to use the PLL_BASE with the BUFG. Additionally many designs may be switched to SDR data rates and use the higher performance BUFPLL clock buffer with the PLL and ISERDES2 or OSERDES2.

Designs requiring phase shifting will continue to be supported for the DLL outputs of the DCM. The following DCM_SP outputs are associated with the DLL and can still be used: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34102 Spartan-6 Low Power - Bitstream Generation not supported in 11.4 N/A N/A
AR# 34675
Date 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • Digital Clock Manager (DCM) Module