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AR# 34722

11.4 EDK, MPMC v5.04.a - How do I create multiple MPMC designs in Virtex-6 FPGA?


How do I use multiple Virtex-6 FPGA designs in MPMC?


The easiest manner to create a multiple MPMC design is to use the MPMCintegrated MIG flow to generate independentsingle-controllerMIG designs. The integrated flow will then manage each controller's UCF automatically, removing the need to make each set of constraints unique.

Each MPMC will require its own Clock Generator core due to the use of phase shifting logic in the MPMC MIG PHY.

Note that banks between the two controllers should not overlap or cross between controllers. The multiple controller MIG flow can be used first to determine which banks can be used before creating the individual MIG projects.
AR# 34722
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • EDK - 11.3
  • EDK - 11.4
  • EDK - 11.5
  • Multi-Port Memory Controller (MPMC)
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