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AR# 34740

MIG Virtex-6 DDR2/DDR3 - PHY Initialization and Calibration

Description

The PHY logic contains state logic for initializing the SDRAM memory after power-up and performs timing training of the read and write data paths to account for system static and dynamic delays.This section of the MIG Design Assistant focuses on the initialization and calibration (timing training) performed by the PHY at power-up.

The Virtex-6 Memory Interface Solutions User Guide (UG406)includes a detailed section on the PHY logic.Please review this material within the DDR2/DDR3 SDRAM Memory Interface Solution > Core Architecture >PHY section:
http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

The following diagram shows the Virtex-6 PHY sequence for initialization and calibration:

When calibration completes successfully cal_done asserts. For detailed information on each stage, see the following:

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
35094 MIG Virtex-6 and 7 Series DDR3 - Write Leveling N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
35163 MIG 7 Series and Virtex-6 DDR2/DDR3 - Per-Bit Deskew N/A N/A

Associated Answer Records

AR# 34740
Date Created 05/24/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG