The PHY logic contains state logic for initializing the SDRAM memory after power-up and performs timing training of the read and write data paths to account for system static and dynamic delays.This section of the MIG Design Assistant focuses on the initialization and calibration (timing training) performed by the PHY at power-up.
The Virtex-6 Memory Interface Solutions User Guide (UG406)includes a detailed section on the PHY logic.Please review this material within the DDR2/DDR3 SDRAM Memory Interface Solution > Core Architecture >PHY section:
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The following diagram shows the Virtex-6 PHY sequence for initialization and calibration:
When calibration completes successfully cal_done asserts. For detailed information on each stage, see the following: