We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34743

MIG Virtex-6 DDR2/DDR3 - Debugging Calibration Failures


The PHY logic contains state logic for initializing the SDRAM memory after power-up and performs timing training of the read and write data paths to account for system static and dynamic delays. Successful completion of this calibration process is denoted by the assertion of phy_init_done. When phy_init_done does not assert, there are various design aspects that must be analyzed. This section of the MIG Design Assistant focuses on the proper debug process for root causing calibration failures (phy_init_done does not assert).

NOTE: This Answer Record is contained in a series of MIG hardware debug Answer Records and assumes you are running the MIG Example Design with the Debug Port Enabled. It is best to start at the beginning of this recommended hardware debug flow; see (Xilinx Answer 34588).

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Calibration often fails due to:
  • Changes to the output MIG UCF/Pin-Out, RTL, Parameters.
  • Board related issues such as not adhering to the Memory Implemenation Guidelines specified for the MIG design.
  • Not running SI Simulations using IBIS models.

The first steps in any calibration debug is to:

Once the design and board have been verified, the next step is to determine during which calibration stage, calibration fails.
  • For general information on the different calibration stages, see (Xilinx Answer 34740).
  • For information on determining the calibration stage that caused phy_init_done to not assert (signifying a calibration failure), see (Xilinx Answer 35169).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
35094 MIG Virtex-6 and 7 Series DDR3 - Write Leveling N/A N/A

Associated Answer Records

AR# 34743
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • MIG