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Xilinx Implementation Tools Solution Center

The Implementation Tools Solution Center is available to address all questions related to implementation tools.

Design Assistant

Xilinx Implementation Tools Solution Center - Design Assistant

Please refer to the following to learn more about designing with the Xilinx Implementation Tools or to find help on debugging an issue you are currently encountering.

NOTE: This answer record is part of the Xilinx Implementation Tools Solution Center (Xilinx Answer 34752). The Xilinx Implementation Tool Solution Center is available to address questions related to Xilinx Implementation Tools.


The Xilinx Implementation Tools have four major functional areas:

For the MAP section of the Xilinx Implementation Tools Design Assistant, see (Xilinx Answer 35438).
In this context MAP refers to the front end and back end of the MAP application which also performs packing and placement. The front end involves the processing of the input logical netlist which can involve retargetting logical instances to newer symbols, the trimming of unused logic and optimization of constant logic, expanding symbols into one or more other symbols and running Logical DRC (LIT messages) to check for issues with the logical netlist. At the back end Physical DRC (PhysDesignRules messages) checks the physical design implementation and finally the printing of the map report (.mrp file) which includes device utilization and other information. MAP also covers the resynthesis options Global Opt which optimized the logical netlist on the front end and Logic Opt that optimizes the physical implementation at the back end.

For the PACK section of the Xilinx Implementation Tool Design Assistant, see (Xilinx Answer 35439).
Packing is the conversion of symbols from the logical netlist into physical elements, either BELs or Components. BELs (Basic Element of Logic) are handled by the placer before a component is assembled, i.e. a LUT or FF BELs will be manipulated by the placer before being assembled into a Slice component. The PACK process begins with Directed packing which assembles components and macros based on packing constraints and also assembles system macros based on connectivity, i.e. carry chain system macros are built at this time to align the carry structure. Packing continues with Delay-Based LUT Packing phase which constructs physical LUTS from logical LUTs, LUTRAM and SRLs. LUT-FF pairs are also created as single entities. At this point timing models are built for the physical implementation and the placement phases are run. After placement PACK constructs components from the placed BELs.

For the PLACE section of the Xilinx Implementation Tool Design Assistant, see (Xilinx Answer 35440).
Placement refers to arrangement of BELs and Components into physical sites on the devices such that routing is feasible and can meet timing constraints. The placement process begins with some feasibility checks and then I/O and clock components are placed together because of their interdependence. A second phase of clock placement is run to constrain the clock loads so that all clocking restrictions are met before general placement begins. A clock distribution report is printed at this point so that the automatic floorplanning of the design can be observed. Various optimizations are run along the way. Phase X.8 (Global Placement) is the general placement phase and it is at this point that the placer attempts to entirely fit the design. If the design is difficult to fit, multiple passes and/or slow run time may be observed. A final placement verification is run before the design is passed back to the packer for final component creation.

For the ROUTE section of the Xilinx Implementation Tool Design Assistant, see (Xilinx Answer 35441).
Routing refers to the creation of pin to pin connections between components that completes the physical implementation of the design. The router needs to find routing resources that complete all connections while meeting all timing constraints. This can be made difficult if the design is either congested, has aggressive timing constraints or if the router has to work with a poor placement. Long run time can be attributed to one or a combination of these factors.


Documentation

Xilinx Implementation Tools Solution Center - Documentation

Please refer to the following documentation when using Xilinx Implementation Tools.

NOTE: This answer record is part of the Xilinx Implementation Tools Solution Center (Xilinx Answer 34752). The Xilinx Implementation Tools Solution Center is available to address questions related to Xilinx Implementation Tools.


User Guides/Manuals

UG628 - Command Line Tools User Guide
UG625 - Constraints Guide

Quick Start Guides and Tutorials

UG657 - ISE Quick Start Tutorial
UG695 - ISE In-Depth Tutorial
UG689 - SmartXplorer for ISE ProjNav Users Tutorial
UG688 - SmartXplorer for Command Line Users Tutorial

Virtex-6 Guides

DS150 - Virtex-6 Family Overview
UG361 - Virtex-6 SelectIO User Guide
UG362 - Virtex-6 Clocking User Guide
UG365 - Virtex-6 Packaging and Pinout Specification
UG623 - Virtex-6 Libraries Guide

Spartan-6 Guides

DS160 - Spartan-6 Family Overview
UG381 - Spartan-6 SelectIO User Guide
UG382 - Spartan-6 Clocking User Guide
UG385 - Spartan-6 Packaging and Pinout Specification
UG615 - Spartan-6 Libraries Guide

Virtex-5 Guides

DS100 - Virtex-5 Family Overview
UG190 - Virtex-5 User Guide
UG195 - Virtex-5 Packaging and Pinout Specification
UG621 - Virtex-5 Libraries Guide

Virtex-4 Guides

DS112 - Virtex-4 Family Overview
UG070 - Virtex-4 FPGA User Guide
UG072 - Virtex-4 Packaging and Pinout Specification
UG619 - Virtex-4 Libraries Guide

Spartan-3 Guides

UG331 - Spartan-3 Family User Guide
DS529 - Spartan-3A Data Sheet
UG613 - Spartan-3A Libraries Guide
DS312 - Spartan-3E Data Sheet
UG617 - Spartan-3E Libraries Guide
DS099 - Spartan-3 Data Sheet
UG607 - Spartan-3 Libraries Guide


Top Issues

Xilinx Implementation Tools Solution Center - Top Issues

The following Answer Records cover current known issues as well as commonly asked questions related to Xilinx Implementation Tools.

NOTE: This answer record is part of the Xilinx Implementation Tool Solution Center (Xilinx Answer 34752). The Xilinx Implementation Tool Solution Center is available to address know issues and common questions related to Xilinx Implementation Tools.


Known Issues
(Xilinx Answer 32147) ISE Design Suite 11 - Known Issues

Virtex-6 FPGA Top Issues
(Xilinx Answer 32929) 11.x Design Suite Known Issues related to the Virtex-6 FPGA
(Xilinx Answer 34693) Patch available for LUTRAM trimming issue introduced by ISE 11.5
(Xilinx Answer 33743) Change in trimming behavior related to IBUFDS_GTXE1 components may affect Synplify Pro designs
(Xilinx Answer 34120) Inversion not pushed into Output FF input unless IOB=FORCE is used
(Xilinx Answer 34352) Constant optimization of LUT6_2 inputs mishandled leading to errors

Spartan-6 FPGA Top Issues
(Xilinx Answer 32651) ISE Design Suite 11 Update Known Issues related to Spartan-6 FPGA
(Xilinx Answer 33153) Incorrect WARNING:ParHelpers:79 message

High Frequency Issues
(Xilinx Answer 23990) Master Answer Record for MAP Trimming Issues
(Xilinx Answer 23363) Master Answer Record for MAP application crashes
(Xilinx Answer 29711) Master Answer Record for debugging ERROR:Pack:679 failures
(Xilinx Answer 34270) An "ERROR:Pack:1107" message occurs in ISE 11.4 without detailed information
(Xilinx Answer 25058) "ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB"
(Xilinx Answer 33632) Place:1018 error does not adequately describe the cause of the error