The following Answer Records cover current known issues as well as commonly asked questions related to Xilinx Implementation Tools.
NOTE: This answer record is part of the Xilinx Implementation Tool Solution Center (Xilinx Answer 34752). The Xilinx Implementation Tool Solution Center is available to address know issues and common questions related to Xilinx Implementation Tools.
(Xilinx Answer 32147) ISE Design Suite 11 - Known Issues
Virtex-6 FPGA Top Issues
(Xilinx Answer 32929) 11.x Design Suite Known Issues related to the Virtex-6 FPGA
(Xilinx Answer 34693) Patch available for LUTRAM trimming issue introduced by ISE 11.5
(Xilinx Answer 33743) Change in trimming behavior related to IBUFDS_GTXE1 components may affect Synplify Pro designs
(Xilinx Answer 34120) Inversion not pushed into Output FF input unless IOB=FORCE is used
(Xilinx Answer 34352) Constant optimization of LUT6_2 inputs mishandled leading to errors
High Frequency Issues
(Xilinx Answer 23990) Master Answer Record for MAP Trimming Issues
(Xilinx Answer 23363) Master Answer Record for MAP application crashes
(Xilinx Answer 29711) Master Answer Record for debugging ERROR:Pack:679 failures
(Xilinx Answer 34270) An "ERROR:Pack:1107" message occurs in ISE 11.4 without detailed information
(Xilinx Answer 25058) "ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB"
(Xilinx Answer 33632) Place:1018 error does not adequately describe the cause of the error