For designs that use the BUFIO2 to route a clock to the input of a PLL or DCM, the feedback path is not properly routed. The BUFIO2 input routing is not correctly delay matched to the BUFIO2FB feedback path. The routing from the Global Clock pins to the BUFIO2, which is inferred, does not route through the ILOGIC2 logic resource to match the feedback path when using BUFIO2FB. For designs that do not use BUFIO2FB, this may not be an issue.
ISE Design Suite 11.5 and earlier does not properly route this feedback path. The issue will be fixed in ISE Design Suite 12.1 and later.
It is possible to manually route the input path through the ILOGIC2 within FPGA_EDITOR. When manually routing, route through the same ILGOGIC2 used by the BUFIO2FB and check to make sure the BUFIO2 and GCLK are located within the same BUFIO2 Clocking Region. Global clock buffers in banks 0 or bank 2 may require the BUFIO2 to be moved as well.
For assistance with implementing this manual route, please contact Xilinx Technical Support.