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There is a black-box submodule in the design which is fed with an EDIF/NGC netlist. The following errors and warnings are issued during Translate:
"ERROR:NgdBuild:770 - IBUF 'b_IBUF' and IBUF 'b_ibuf' on net 'b_IBUF' are linedup in series. Buffers of the same direction cannot be placed in series. WARNING:NgdBuild:463 - input pad net 'b_IBUF' has an illegal input buffer ERROR:NgdBuild:925 - input net 'b_IBUF' is connected to the incorrect side ofbuffer(s): pin O on block b_IBUF with type IBUF ERROR:NgdBuild:924 - input pad net 'clk_BUFGP' is driving non-buffer primitives: pin C on block h with type FDR, pin C on block g with type FD, pin O on block clk_BUFGP/BUFG with type BUFG ERROR:NgdBuild:809 - output pad net 'e' has an illegal load: pin I1 on block Mxor_g_xor0000_Result1 with type LUT2 ERROR:NgdBuild:455 - logical net 'h' has multiple driver(s): pin Q on block h with type FDR, pin PAD on block h.PAD with type PAD"
How can I resolve these errors?
These errors are issued because the submodule EDIF/NGC netlist contains IBUFs/OBUFs. XST also adds IBUFs and OBUFs to the top level, so that they are lined up or the pads are driving/being driven by non-buffer components.
When an EDIF/NGC netlist is used as a submodule of another design, the following conditions must be met:
If the input/output ports of the submodule are connected to the top module ports directly, like port1in the following figure, the IBUFs/OBUFs can be put in the submodule,but theXST property "Read Cores"has tobe checked. Then,XSTwill read the netlistin the project directory or a location specified in "Cores Search Directories" and will not add extra IBUFs/OBUFs on these top level ports.
If theinput/output ports of the submodule are NOT connected to the top module ports directly, like port2 inthe following figure, the IBUFs/OBUFs must not be put in the submodule.
The following are some solutions to this problem.
Disable IBUF/OBUF insertion when you generate the submodule netlist. Add all IBUFs/OBUFsto the top level.
For XST, go to Synthesis Properties -> Xilinx Specific Options -> uncheck "Add I/O Buffers"
For Synplify Pro, go to Implementation Options -> Device tab -> check "Disable I/O Insertion"
Selectively disableIBUF/OBUF insertion onthe input/output ports that are NOT connected to the top module ports directly.
For XST, use "buffer_type" constraint. Please refer to XST User Guide.
If theIBUF/OBUFs are instantiated in the submodule, disablingIBUF/OBUF insertiondoes not remove the buffers from the submodule. If this is the case, remove theIBUF/OBUFs instantaiation from the submodule and instantiate them in the top level.