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AR# 34775

FIFO generator support for non power of 2 depth

Description


What is the support for non power of 2 depth in FIFO Generator?

Solution

This is part of the FIFO addressing scheme. The  Xilinx FIFO generator used Gray code counters for addressing. 

Because gray counters have to be designed for mod (2n), the maximum FIFO depth must also be power of 2. 

However in binary any depth is permitted.

 

Power of 2 depth is easy to handle. 

Non-power of 2 depth increases the complexity in handling gray counters for FULL/EMPTY generation for independent clock FIFO. 

This is also due to the nature of gray coding in pointers for cross clock domain.

 

The size of the FIFO refers to the amount of data available at a given time. 

In asynchronous FIFO this depends on both read and write clock domain frequencies and the amount of data written and read (data rate). 

Data rate can vary depending on the two clock domain operation and requirement (and of course frequency!).

The worst case condition is the maximum data rate difference between the read and write clock. 

This can happen when the data rate of the writing operation is the maximum and for the read operation the data rate is the minimum.

 

Further explanation:

 

Two types of counters are used as FIFO pointers for addressing - binary counters and Grey counters.

Each of these methods has advantages and dis-advantages. 

Synchronization advantages and pitfalls between the read and write clock domain is the decisive factor in choosing right counter design as pointers.

 

Binary counter is a natural counter and hence easy to design and implement. 

This counter works very well in addressing FIFO. 

 

Example:

There are total 16 memory locations in the FIFO.

To address these 16=24 locations a 4 bit counter is required. (Actually you will need to design a 5 bit counter. This will be explained later in the article) 

 

Binary code patterns are not unidistance. 

The number of bits changing from one count to another count can be more than one. 

For example, bits changing from 0001 to 0010 are 2.

In the worst case scenario, all 4 bits can change simultaneously, as in 0111 to 1000. 

Changing bits (nothing but pointers) will need to be synchronized with the other clock domains to generate the empty and full conditions.

If the synchronization clock edge becomes active in between the transition of binary bits, say, 0111 to 1000, then metastability can occur with any of the four bits or with all of the bits. 

This metastable state can be resolved to any four-bit count value, prediction of which is almost impossible. 

The pointer value synchronized with the other clock domain might become entirely different than intended. 

This is the biggest drawback of using binary counters as FIFO pointers.

One way to counter this problem is to use a holding register for synchronization. 

This uses handshaking signals to communicate between the synchronizer and the clock domain.

Binary count values from original clock domain are sampled and held in the holding register and a ready signal is passed to the other clock domain.

Upon receipt of the ready signal, the other clock domain receives the count values and sends back a synchronized acknowledgement. 


The original clock domain resamples another count value.


 

Gray numbers are unidistance numbers.

Unlike binary numbers only one bit changes from one count to another count. 

Gray pointers also have the problem of metastability while synchronizing with other clock domains, though this is minimized by the fact of one bit change. 

The Metastability condition on one bit causes a +/- 1 count error which is better than the +/-8 count error in binary pointers. 

Because of this minimized error, gray counters are generally used as FIFO pointers.

 

Here is the trade off between binary counter and gray counter as pointers:

 

Binary pointers pose multibit synchronization problems. Gray counter minimizes this problem.

A gray counter designed for any mod number other than 2n (n being number of bits), does not remain as gray code.

Hence we must design a mod 2n gray counter. 

This implies that the FIFO memory location must also be 2n. 

However, binary counters can be designed to have any mod number so FIFO memory locations can also be any arbitrary number.


Because binary arithmetic is natural, it is easy to calculate and implement "almost empty" and "almost full" with binary numbers.

The sampling technique using holding register and handshaking control is advantageous in passing any arbitrary multibit values or pointers. 

However in gray counters an arbitrary value is not possible, they either increment or decrement.


Because a gray counter has to be designed for mod (2n), FIFO depth (maximum) must also be power of 2, but in binary any depth is permitted.

Use of a binary pointer introduces latency of a minimum of 2 clock cycles in synchronization.

AR# 34775
Date Created 03/16/2010
Last Updated 03/30/2015
Status Active
Type General Article
IP
  • FIFO Generator