AR# 34783

LogiCORE IP 10-Gigabit Ethernet MAC v9.3 - Virtex-6 FPGA block RAM parameterization might result in memory collisions during simulation and erroneous operation


When I target Virtex-6 FPGA in the 10-Gigabit Ethernet MAC version 9.3 and earlier, block RAM instances do not comply with all asynchronous clocking conflict avoidance requirements as described in the Virtex-6 FPGA Memory Resources User Guide (UG363):

This problem only exists when the example design local link FIFO is used and could result in memory collisions and erroneous behavior.


This issue has been corrected in the 10-Gigabit Ethernet MAC version 9.3 rev1 and later available starting in ISE design tools 11.5.

Linked Answer Records

Master Answer Records

Associated Answer Records

AR# 34783
Date 05/23/2014
Status Archive
Type General Article
Devices More Less
Tools More Less