This section of the MIG Design Assistant will guide you to details on the User Interface for the Virtex-6 and 7 series FPGAs DDR3/DDR2 designs. Please select from the options below to find information related to your specific question.
NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.