A possible causeforthe PCIe device not being recognized by the systemmight be due tothe FPGAnot configuringin time to be enumerated and configured by the system software (BIOS).
It is also possible that late FPGA configuration might impact link training which causes the core to notlink up.
NOTE:This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536).The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe.Whether you're starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.
A quick test for this is after the system boots from power on, issue a warm restart and then see if the endpoint is recognized. During a warm restart the system power remains on to the board so the FPGA does not have to reconfigure.
If after a warmrestart the device is recognizedby the systemthen the problem could be due to FPGA configuration time. See (Xilinx Answer 34806) regarding software tools that can be used to see if the device is recognized by the system.
In standard systems for PCI Express, when the system is powered up, configuration software running on the processor starts scanning the PCI Express bus to discover the machine topology.
The process of scanning the PCI Express hierarchy to determine its topology is referred to as the enumeration process. The root complex accomplishes this by initiating configuration transactions to devices as it traverses and determines the topology.
All PCI Express devices are expected to have established the link with their link partner and be ready to accept configuration requests during the enumeration process. As a result, there are requirements as to when a device needs to be ready to accept configuration requests after power up; if the requirements are not met, the following occurs:
The User Guides for each product contains a chapter called "FPGA Configuration". This chapter goes into details about this issue whichishelpful in solving the problem. It also list configuration times for each FPGA based on the type of configuration scheme used.
12/08/2010 - Updated description to include link up
08/13/2010 - Initial Release