I have a design that synthesized successfully when I target devices older than Spartan-6/Virtex-6 FPGA. However for Spartan-6/Virtex-6 FPGA, I encounter the following error. Why?
ERROR:HDLCompiler:661 - "<verilog file>" Line #: Non-net port clk_i cannot be of mode input
XST is using a new parser starting with Virtex-6 and Spartan-6 FPGA which has enhanced language coverage and follows stricter LRM guidelines.
The error appears to occur when using the "`default_nettype none" to turn off automatic inference of wires in the design.
XST for Spartan-6 / Virtex-6 FPGA correctly issues an error for designs that declare port signals but do not implicitly declare wires for them. For example, the following code for a blackbox will issue the above error:
`default_nettype none // Do not to infer wiring.
input clk ,//
This is in adherence to section 19.2 of the Verilog 2001 LRM.
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