This section of the MIG Design Assistant focuses on the Controller Responsibilities of the MIG 7 series andVirtex-6 DDR3/DDR2 designs. The Memory Controller (MC) is responsible for receiving all requests from the User/Native Interface and storing them in a logical queue.In processing these requests, the MC ensures that all functional and timing requirements of the JEDEC standard/memory device are met. The MC only receives Read/Write commands, but must ensure that all required commands to complete Reads/Writes are sent (Refresh, Activate, Precharge). Please select from the options belowto find information related to your specific question.
NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
For information on available DDR Commands MIG 7 Series and Virtex-6 DDR3/DDR2 design, see:
(Xilinx Answer 34941) - Available DDR Commands
For information on the Auto-Refresh Counter for the MIG 7 Series and Virtex-6 DDR3/DDR2 design, see:
(Xilinx Answer 34371) - Auto-Refresh Counter
For information on the PHY-Like Controller Responsibilities of the MIG Virtex-6 DDR3/DDR2 design, see:
(Xilinx Answer 34903) - PHY-Like Controller Responsibilities
For information on the Reordering Logic of the MIG 7 Series and Virtex-6 DDR3/DDR2 design, see:
(Xilinx Answer 34942) - Reordering Logic
For Information on how many commands can be stored at a time, see:
(Xilinx Answer 35410) - Storing Commands
For information on how many banks can remain open at a time, see:
(Xilinx Answer 36883) - Can multiple banks be open at the same time? If so, how many?
09/18/2012 - Minor update
09/07/2012 - Added MIG 7 Series
08/24/2010 - Added link to Answer Record 36883