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AR# 34924

Partial Reconfiguration - How does the Xilinx Partial Reconfiguration Solution work?


What are the main steps of the Xilinx Partial Reconfiguration (PR) Solution Flow and how does it work?


Partial Reconfiguration is the modification of an operating FPGA design by loading a partial configuration file.

The Dynamic Modules are translated into partial BIT files which define the new hardware function.

First, an initial design is Implemented in the Partial Reconfiguration flow.

This design will contain the Static Logic and one or more Dynamic modules.

Once this configuration is implemented then those modules are promoted and used as "golden" modules for future modifications. 

After this, new versions of the dynamic modules can be created and uploaded in the functioning design without stopping its task.

For more detailed information, please see UG702.


Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
61284 Partial Reconfiguration - Is it possible to reuse Reconfigurable Modules with a new Static Design? N/A N/A
AR# 34924
Date 09/30/2014
Status Active
Type General Article
  • FPGA Device Families
  • PlanAhead
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