UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34933

11.x Timing Analyzer - The slack for fastest path analysis of OFFSET OUT constraint does not make sense

Description

In the timing report, the slack for the fastest path analysis of the OFFSET OUT constraint comes from the following expression:

clock arrival + clock path + data path - clock uncertainty

This expression does not make sense for a "slack" because it is not a difference between "requirement" and "actual". 

This just calculates a "delay" value for the fastest path in the fast corner.

When the result of this expression is a negative value, it will be marked as a violation, which could cause confusion as it is actually not a timing error.

Solution

Starting in ISE Design Suite 12.1, this "slack" has been changed to "delay" for fastest path analysis of the OFFSET OUT constraint.

In versions prior to 12.1, please ignore any negative "slack" value in the fastest path analysis.

AR# 34933
Date Created 03/25/2010
Last Updated 01/12/2015
Status Active
Type General Article
Tools
  • ISE Design Suite - 11
  • ISE - 10