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AR# 34934

MIG Spartan-6 MCB - Is it possible to share PLL and BUFPLL_MCB resources in multi-controller designs?

Description

Spartan-6 devices include up to four Memory Controller Blocks (MCBs). For multi-controller (multi-MCB) designs, combining or sharing PLL and BUFPLL_MCB saves resources.

Note:This Answer Record is a part of the Xilinx MIG Solution Center(Xilinx Answer 34243).The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

If the MCBs are on the same side of the device, the BUFPLL_MCB must be shared, which requires the interfaces to run at the same frequency.You can find anexample diagram in the Spartan-6 FPGA Memory Controller User Guide(UG388). For more information, please see Figure 3-3: Recommended System and Calibration Clock Distribution.

If the MCBs are on both sides of the device, the PLL can be shared. The one PLL then drives two BUFPLL_MCBs (one on each side of the device).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43319 MIG Spartan-6 MCB - Clocking and Reset N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43319 MIG Spartan-6 MCB - Clocking and Reset N/A N/A
43318 MIG Spartan-6 MCB - How to Verify that Pin-out Requirements Are Met N/A N/A
AR# 34934
Date Created 04/05/2010
Last Updated 02/12/2013
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
IP
  • MIG