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AR# 34936

11.5 ISIM - "FATAL_ERROR:Simulator:CompilerAssert.h:40:1.64 - Internal Compiler Error in file ../src/VhdlExpr.cpp at line 5239..."

Description

Why does the following error occur when I perform a behavioral simulation of my design?

"FATAL_ERROR:Simulator:CompilerAssert.h:40:1.64 - Internal Compiler Error in file ../src/VhdlExpr.cpp at line 5239 Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support."

Solution

Solution 1

This fatal error occurs when the "others" keyword is used in the if/elsif statements with an array aggregate as shown below:

if (ds1_a5 = (others=>'1') and ds1_a4 = (others=>'0') and ds1_a3 = (others=>'0')) then
..
..
..

This is illegal according to IEEE VHDL LRM 7.3.2.2. The correct way is shown below:

if (ds1_a5 = "1111111111" and ds1_a4 = "0000000000" and ds1_a3 = "0000000000") then

OR

if (ds1_a5 = (ds1_a5'range=>'1') and ds1_a4 = (ds1_a4'range=>'0') and ds1_a3 = (ds1_a3'range=>'0')) then

This issue is currently under investigation. In a future release of ISE Design Suite, a clear error message is to be printed out instead of a fatal error.

Solution 2

This fatal error has been observed when declaring a subtype in the following manner:

function f(Arg:bit_vector) return integer is

subtype s_ArgRange is integer range Arg'range;
variable Result: s_ArgRange;
begin
end f;

To work around this issue, change the code above from:

subtype s_ArgRange is integer range Arg'range;
variable Result: s_ArgRange;

to:

variable Result: integer range Arg'range;

This issue has been fixed in ISE Design Suite 12.2.
To download and install the latest version of ISE Design Suite, visit the Download Center at http://www.xilinx.com/support/download/index.htm
AR# 34936
Date Created 06/11/2010
Last Updated 11/03/2010
Status Active
Type Design Advisory
Tools
  • ISE Design Suite - 11.5
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
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