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Xilinx Virtex-6 FPGA Solution Center

The Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.

Design Assistant

Xilinx Virtex-6 FPGA Solution Center - Design Assistant

The Virtex-6 FPGA Design Assistant walks you through the recommended design flow for Virtex-6 FPGA while debugging commonly encountered issues for clocking, fabric, and block RAM/FIFO design. The Design Assistant not only provides useful design and troubleshoot information, but also points you to the exact documentation you need to help you design efficiently with Virtex-6 FPGA.

NOTE: This answer record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963). The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.


First, select the design phase where you have a question or are troubleshooting an issue related to your Virtex-6 FPGA design. This ensures the Design Assistant points you to the information you need to move forward with your design.

(Xilinx Answer 34965) - Getting Started with the Virtex-6 FPGA
(Xilinx Answer 34977) - Designing for the Virtex-6 FPGA
(Xilinx Answer 37710) - Board Level Considerations
(Xilinx Answer 37211) - Troubleshooting - Clocking, Fabric, block RAM/FIFO

* For troubleshooting of other areas of FPGA design, please see the Top Issues and Design Assistant areas of other available solutions centers.


Documentation

Virtex-6 FPGA Documentation - What documentation should I review to find out if the Virtex-6 FPGA features and specifications are right for my system?

What Xilinx documentation should I review to help me understand whether the Virtex-6 FPGA specifications and features are right for my system?

NOTE: This answer record is part of the Xilinx Virtex-6 Solution Center (Xilinx Answer 34963). The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.


The Xilinx Documentation Center contains all Virtex-6 FPGA related documentation:
http://www.xilinx.com/support/documentation/virtex-6.htm

The following documents are available:

  • Virtex-6 Family Overview
  • Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
  • Virtex-6 Errata
  • Virtex-6 User Guides

Use the Virtex-6 Family Overview to understand the features available in the Virtex-6 FPGA device family and view the differences among the devices within the Virtex-6 FPGA family to assist in product selection.

Use the Virtex-6 FPGA Data Sheet to review the DC and Switching Characteristic specifications for the Virtex-6 family.

Review the Virtex-6 Errata to determine whether the device you are considering has any exceptions to data sheet specifications.

Review the Virtex-6 User Guides to understand usage details for the Virtex-6 FPGA resources.


Design Advisories

Design Advisory Master Answer Record for Virtex-6 FPGA

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the Virtex-6 FPGA and related issues that impact Virtex-6 FPGA designs.


Design Advisory Alerted on April 8, 2013:
04/05/2013 (Xilinx Answer 45166) Updated Design Advisory for Virtex-6 FPGA GTH Transceiver to include the updated RX_P1_CTRL attribute value 

Design Advisory Alerted on August 13, 2012:
08/15/2012 (Xilinx Answer 51145) Design Advisory - 14.2 iMPACT - Indirect Programming on Virtex-6 causes tool to crash without warning

Design Advisory Alerted on May 21, 2012:
05/17/2012 (Xilinx Answer 47938) Design Advisory for Virtex-6 FPGA - Designs usingOPAD Tioop/Tiotpmust be re-run through timing analysis

Design Advisory Alerted onFebruary 13, 2012:
01/25/2012 Update to(Xilinx Answer 42444) Design Advisory for Virtex-6 FPGA - Designs using 18K/36K block RAM or 18K/36K FIFO must be re-run through timing analysis

Design Advisory Alerted on January 16, 2012:
01/13/2012 (Xilinx Answer 45166) Design Advisory for Virtex-6 GTH Transceiver on burst of errors at startup and RXRECCLK not toggling at startup

Design Advisory Alerted on December 19, 2011:
12/13/2011(Xilinx Answer 43591)Updated Design Advisory for Virtex-6 FPGA GTH Transceivers on RXBUFRESET-related initialization sequence and BUFFER_CONFIG_LANEx issues to include fix information for ES Silicon

Design Advisory Alerted on November 21, 2011:
11/21/2011 (Xilinx Answer 44174)Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup

Design Advisories Alerted onSeptember 19, 2011:
09/19/2011(Xilinx Answer 43829)Design Advisory for Virtex-6 FPGA GTH Transceivers -Incorrect RXBUFRESET connections in the wrapper in x4 Mode

Design Advisories Alerted onAugust 22, 2011:
08/22/2011(Xilinx Answer 43591)Design Advisory for Virtex-6 FPGA GTH Transceivers - Updates required to address RXBUFRESET-related initialization sequence and BUFFER_CONFIG_LANEx issues

Design Advisories Alerted onAugust 8, 2011:
08/08/2011(Xilinx Answer 43346) Design Advisory for Virtex-6 GTH - Recommendation for Non-retimed 10G+ Optical Interfaces (e.g., SFP+ and QSFP)
08/08/2011 (Xilinx Answer 42682)Design Advisory for Virtex-6 FPGA - 13.x iMPACT - eFUSE key programming incorrect when target FPGA is not the only device in the JTAG chain

Design Advisories Alerted onJuly 11, 2011:
07/08/2011 (Xilinx Answer 42444) Design Advisory for Virtex-6 FPGA - Designs using 18K/36K block RAM or 18K/36K FIFO must be re-run through timing analysis
07/07/2011 (Xilinx Answer 41821) Design Advisory for Virtex-6 FPGA - BitGen Option -g Next_Config_Addr: Default Value Changed
07/07/2011 (Xilinx Answer 41099)Design Advisory for Virtex-6 FPGA - Synchronous FIFOs must have reset synchronized to RDCLK/WRCLK

Design Advisories Alerted onJuly 6, 2011:
07/01/2011 (Xilinx Answer 42444) Design Advisory for Virtex-6 FPGA - Designs using 18K/36K block RAM or 18K FIFO must be re-run through timing analysis
06/30/2011 (Xilinx Answer 42682)Design Advisory for Virtex-6 FPGA - 13.x iMPACT - eFUSE key programming incorrect when target FPGA is not the only device in the JTAG chain
04/11/2011 (Xilinx Answer 41099) Design Advisory for Virtex-6 FPGA - Synchronous FIFOs must have reset synchronized to RDCLK/WRCLK

Design Advisories Alerted on March 21, 2011:
03/18/2011 (Xilinx Answer 40885) Updated Design Advisory for Virtex-6 FPGA Production GTH Transceivers to include GTH TXUSERCLKOUT/RXUSERCLKOUT operational guideline.

Design Advisories Alerted on March 7, 2011:
03/04/2011 (Xilinx Answer 40885) Design Advisory for Virtex-6 FPGA - Production GTH Transceivers

Design Advisories Alerted on October 18, 2010:
10/11/2010 (Xilinx Answer 38132) Virtex-6 FPGA MMCM Design Advisory - MMCM BANDWIDTH attribute requirement
10/11/2010 (Xilinx Answer 38133) Virtex-6 FPGA MMCM Design Advisory - Restriction for DIVCLK_DIVIDE value when Fclkin > 315 MHz
09/27/2010 (Xilinx Answer 38134) Virtex-6 Configuration - PROGRAM_B pin held Low prior to power up does not delay configuration
09/07/2010 (Xilinx Answer 36642) Virtex-6 System Monitor - Maximum DCLK frequency revised down to 80 MHz

Design Advisories Alerted on August 30, 2010:
08/27/2010 (Xilinx Answer 37667) Virtex-6 FPGA -1L Industrial Grade Vccint Specification Change

Design Advisories Alerted on March 22, 2010:
03/19/2010 (Xilinx Answer 34859) Virtex-6 FPGA Block RAM Design Advisory - Address Space Overlap
02/11/2010 (Xilinx Answer 33849) Virtex-6 FPGA MMCM - New Requirements for all MMCMs, VCO minimum frequency, and CLKBOUT_MULT_F values
01/22/2010 (Xilinx Answer 34164) Virtex-6 11.4 ISE - Virtex-6 FPGA designs must be re-run through implementation in ISE 11.5 or later software

Revision History:

04/05/2013 - Updated Answer Record 45166
09/24/2012 - Minor update; no change to content
08/09/2012 - Added Answer Record 51145
05/17/2012 - Added Answer Record 47938
02/13/2012 - Added Update to Answer Record 42444
01/13/2012 - Added Answer Record 45166
12/13/2011 - Updated Answer Record 43591
12/12/2011 - Updated title for 44174
11/21/2011 - Added Answer Record 44174
09/15/2011 - Added Answer Record 43829
08/18/2011 - AddedAnswer Record 43591
08/01/2011 - Added Answer Record 43346, updated Answer Record 42682
07/07/2011 - Added Answer Record 41821, updated Answer Records 42444 and 41099
07/05/2011 - Added Answer Record 42444, updated Answer Record 41099
06/30/2011 - Added Answer Record 42682
03/18/2011 - Updated Answer Record 40885
03/04/2011 - Added Answer Record 40885
10/14/2010 - Added Answer Records 38134, 36642
10/12/2010 - Added Answer Records 38132, 38133
08/27/2010 - Added Answer Record 37667
03/19/2010 - Initial Release


Answer Number Answer Title Version Found Version Resolved
45166 Design Advisory for Virtex-6 FPGA GTH Transceiver - Incorrect RX_P1_CTRL attribute can cause undesirable RX behavior N/A N/A
43829 Design Advisory for Virtex-6 FPGA GTH Transceivers - Incorrect RXBUFRESET connections in the wrapper in x4 mode N/A N/A
42444 Design Advisory for Virtex-6 FPGA - Designs using 18K/36K block RAM or 18K/36K FIFO must be re-run through timing analysis N/A N/A
41821 Design Advisory for Virtex-6 BitGen Option Change Can Cause Configuration Failures for Bit Files Generated in 13.2 Where 13.1 Files Worked N/A N/A
41099 Design Advisory for Virtex-6 FPGA - Synchronous FIFOs must have reset synchronized to RDCLK/WRCLK N/A N/A
38134 Design Advisory for Virtex-6 Configuration - PROGRAM_B pin held Low prior to power up does not delay configuration N/A N/A
38133 Virtex-6 FPGA MMCM Design Advisory - Restriction for DIVCLK_DIVIDE value when Fclkin > 315 MHz N/A N/A
38132 Virtex-6 FPGA MMCM Design Advisory - MMCM BANDWIDTH attribute requirement N/A N/A
37667 Virtex-6 FPGA -1L Industrial Grade Vccint Specification Change N/A N/A
34859 Virtex-6 FPGA Block RAM Design Advisory - Address Space Overlap N/A N/A
47938 Design Advisory for 14.1 Timing Analysis Virtex-6 - Tioop/Tiotp values have increased in the analysis of OFFSET OUT and FROM:TO constraints N/A N/A
44174 Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup N/A N/A
33849 Virtex-6 FPGA MMCM - New Requirements for all MMCMs, VCO minimum frequency, and CLKFBOUT_MULT_F values N/A N/A
34164 Virtex-6 11.4 ISE - Virtex-6 FPGA designs must be re-run through implementation in ISE 11.5 or later software N/A N/A
51145 Design Advisory - 14.2 iMPACT - Indirect Programming on Virtex-6 causes tool to crash without warning N/A N/A

Top Issues

Virtex-6 - 12.x Software Known Issues related to the Virtex-6 FPGA

This answer record describes the Known Issues for the Virtex-6 FPGA generation used with ISE Design Suite 12.

The following represent a collection of issues that have been identified in the12.x ISE Design Tools and are related to Virtex-6 FPGA. There might be issues which are present and are not listed here. If you discover an issue that is not on this list, please open a WebCase with Xilinx Technical Support.

It is strongly recommended that designs be re-synthesized (and IP cores re-implemented) when re-implementing for production using the software that has production status speed files for the target device. This ensures that the changes to DRCs, timing models, clock topologies, and other fixes in softwareare picked up.

All ISE Design Suite 12.x:

BlockRAM/FIFO

(Xilinx Answer 42444) Design Advisory - Virtex-6 FPGA designs using 18K/36K block RAM or 18K FIFO must be re-run through timing analysis

MMCM

(Xilinx Answer 38132)Virtex-6 FPGA MMCM Design Advisory - MMCM BANDWIDTH attribute requirement
(Xilinx Answer 38133)Virtex-6 FPGA MMCM Design Advisory - Restriction for DIVCLK_DIVIDE value when Fclkin > 315 MHz

ISE Design Suite 12.3:

MMCM

(Xilinx Answer 39029) Virtex-6 MMCM - Incorrect phase shift from MMCM when using negative phase shifts
(Xilinx Answer 34219) Virtex-6 MMCM - Cascaded MMCMs may not work in hardware

ChipScope Pro/IBERT

(Xilinx Answer 37355) 12.2/12.3 ChipScope - IBERT - GTH - Parameter sweep is not supported
(Xilinx Answer 32912) 11.2 ChipScope Analyzer - "ERROR:INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24"
(Xilinx Answer 35420) 12.x/11.x ChipScope IBERT - Using LVDS_25 clock for system clock does not enable DIFF_TERM on input
(Xilinx Answer 33599) 11.x ChipScope Pro - "csejtag - The application failed to start because libCseCore.dll was not found. Re-installing the application may fix this problem."
(Xilinx Answer 37354) 12.2/12.3 ChipScope - IBERT - GTH - In the Analyzer the reset does not always set the error bit count to zero

MIG

(Xilinx Answer 38104) MIG v3.6, Virtex-6 DDR3 - The GUI does not allow AXI RDIMM data width selection
(Xilinx Answer 37997) MIG v3.6 Virtex-6 DDR3 Multi-Controller - GUI only allows single controller generation for CXT -1 devices
(Xilinx Answer 37863) MIG v3.6, Virtex-6 Multi-Controller - Default bank selection for all FF1760 packages results in MAP error

MAP

(Xilinx Answer 37835) 12.2 MAP - MMCM calibration circuit not included when global optimization is turned on

GTX Transceiver

(Xilinx Answer 35681) Virtex-6 GTX Transceiver - MMCM fails to lock and TX/RXRESETDONE fails to assert

PCI Express

(Xilinx Answer 37963) Virtex-6 FPGA Integrated Block Wrapper v2.1 for PCI Express - VHDL Wrapper Not Available for v2.1 Release

-----------------------------------------------------------------------------------------------------------------------------

ISE Design Suite12.2:

Block RAM

(Xilinx Answer 34859) Virtex-6 FPGA Block RAM Design Advisory - Address Space Overlap

Configuration

(Xilinx Answer 35451) iMPACT 12.x - Removing Numonyx J3 (Rev D, F) indirect programming support for Virtex-6 in 12.2

PlanAhead

(Xilinx Answer 35917) 12.1 Virtex-6 PlanAhead - When I import placement, BUFGDLL is not a supported primitive

ChipScope IBERT

(Xilinx Answer 36576) 12.2 ChipScope IBERT - When I do not select the Implement Design option no implementation scripts are created
(Xilinx Answer 34674) 11.x/12.1 ChipScope IBERT - Virtex-6 FPGA GTX: CORE Generator does not list upper GTXE1 quads of SX475T and LX550T
(Xilinx Answer 34683) 11.x/12.x ChipScope, Virtex-6 - IBERT parameter sweep tests show errors in the middle of the eye
(Xilinx Answer 36680) 12.2 CORE Generator - Generating an iBERT core fails with ERROR:sim - Unable to evaluate Tcl command

GTX Transceiver

(Xilinx Answer 37014) Virtex-6 GTX Transceiver: ERROR:MapLib:1226 - GTXE1 - DRC Error when POWER_SAVE is set incorrectly

XAUI

(Xilinx Answer 36228) LogiCORE IP XAUI v9.1 and v9.1 rev1 - Virtex-6 GTX_POWER_SAVE needs to be updated to target ISE 12.2

Embedded Tri-mode Ethernet MAC Wrapper v1.4

(Xilinx Answer 36223) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.4 - When targeting SGMII or 1000BASE-X, DRC error is seen regarding GTX POWER_SAVE

Ethernet 1000BASE-X PCS/PMA or SGMII v10.5

(Xilinx Answer 36957) LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v10.5 - GMII setup/hold errors seen when targeting Virtex-6 HXT

MPMC

(Xilinx Answer 33817) 12.2 EDK, MPMC v6.00.a, Virtex-6 - ERROR:ConstraintSystem:58 - Constraint does not match any design objects

-----------------------------------------------------------------------------------------------------------------------------

ISE Design Suite12.1:

Aurora 64B/66B

(Xilinx Answer 35371) Aurora 64B/66B v4.1 - Release Notes and Known Issues for ISE Design Suite 12.1

Block RAM

(Xilinx Answer 34859) Virtex-6 FPGA Block RAM Design Advisory - Address Space Overlap

MMCM

(Xilinx Answer 36274) 11.5, 12.1 Virtex-6 MMCM - MMCM does not lock after device startup andMMCM reset

I/O

(Xilinx Answer 36082) Virtex-6 SelectIO - DCI Cascade across non-continuous banks is supported in ISE software 12.2
(Xilinx Answer 36320) Virtex-6 - N-side pseudo-differential output driven by OSERDES does not toggle
(Xilinx Answer 35952) Config BitGen - UnusedPin option not pulling up unused I/Os in Virtex-6 devices

MAP/PAR

(Xilinx Answer 35574) 12.1 Project Navigator - The -mt (Enable Multi-Threading) option is greyed out in MAP and PAR Process Properties

Timing Simulation

(Xilinx Answer 35514) 12.1 - Timing simulation issue when targeting Virtex-6 devices

iMPACT

(Xilinx Answer 33942) 11.x iMPACT - When I add a Winbond SPI Flash for Indirect programming, I am prompted for a Data Width. Does Virtex-6 FPGA support x2 or x4 SPI?

Partial Reconfiguration

(Xilinx Answer 35399) 12.1 Virtex-6 FPGA Partial Reconfiguration - RAM contents not written correctly to Partial Bitfiles

ChipScope

(Xilinx Answer 35417) 12.1 ChipScope Pro - Virtex-6Q, Spartan-6Q, and Spartan-6Q LX/LXT devices are not supported in ChipScope Pro tools
(Xilinx Answer 33701) 12.1/11.x ChipScope Pro - IBERT - Virtex-6 - IBERT generation fails on Virtex-6 when I enable 8 or more GTs
(Xilinx Answer 34674) 11.x/12.x ChipScope, IBERT -Virtex-6 GTX, CORE Generator does not list upper GTXE1 quads of SX475T and LX550T
(Xilinx Answer 34683)11.x/12.x ChipScope, Virtex-6 - IBERT parameter sweep tests show errors in the middle of the eye

GTX Transceiver Wizard

(Xilinx Answer 34191) Virtex-6 FPGA GTX Transceiver Wizard - Attribute updates for production silicon

GTX Transceiver

(Xilinx Answer 35055) Virtex-6 FPGA GTX Transceiver - Automatic macro insertion for unused GTX Transceivers

MPMC

(Xilinx Answer 34717) 12.1 EDK, MPMC v6.00.a- ERROR:EDK:1558 - PORT MPMC_Clk_Wr_I0 not found in mpd

MIG

(Xilinx Answer 35742) MIG v3.0-3.4 Virtex-6 DDR2 SDRAM - Incorrect timing on DDR2_RAS_N
(Xilinx Answer 35247) MIG v3.4 Virtex-6 DDR2/DDR3 - Fixed Pin-Out tool does not allow selection of VREF sites
(Xilinx Answer 35252) MIG v3.0-3.4 Virtex-6 DDR3 - REFCLK Frequency (IODELAYCTRL Reference clock) must be 300 MHz for interfaces running between 480-533 MHz
(Xilinx Answer 36503) MIG v3.4 Virtex-6 DDR3 - Cannot see phy_init_done go high in simulation

PCI Express

(Xilinx Answer 33834) Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Use of Component Name "core" Causes Implementation Failures using VHDL Flow
(Xilinx Answer 34009) Virtex-6 FPGA ML605 Board- PCI Express Link Will Not Train; Implementations for PCI Express Must Use the v1.3 Integrated Block Wrapper for PCI Express
(Xilinx Answer 34115) Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - WARNING:Xst:2016 - Found a loop when searching source

Tri-mode Ethernet MAC v1.4

(Xilinx Answer 33195) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Adjusting IDELAYs to meet GMII and RGMII setup and hold requirements

Revision History

09/24/2012 - Minor update; no change to content
07/18/2011 - Updated to include BRAM/FIFO issue
10/22/2010 - Added MMCM (Xilinx Answer 34219)
10/08/2010 - Updated for 12.3
08/02/2010 - Updated for 12.2 and added answer records for 12.1
05/04/2010 - Added GTX Transceiver (Xilinx Answer 35055) and Timing Simulation (Xilinx Answer 35514)
05/03/2010 - Initial 12.1 release