The Virtex-6 FPGA Design Assistant walks you through the recommended design flow for Virtex-6 FPGA while debugging commonly encountered issues for clocking, fabric, and block RAM/FIFO design. The Design Assistant not only provides useful design and troubleshoot information, but also points you to the exact documentation you need to help you design efficiently with Virtex-6 FPGA.
NOTE: This answer record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963). The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.
First, select the design phase where you have a question or are troubleshooting an issue related to your Virtex-6 FPGA design. This ensures the Design Assistant points you to the information you need to move forward with your design.
(Xilinx Answer 34965) - Getting Started with the Virtex-6 FPGA
(Xilinx Answer 34977) - Designing for the Virtex-6 FPGA
(Xilinx Answer 37710) - Board Level Considerations
(Xilinx Answer 37211) - Troubleshooting - Clocking, Fabric, block RAM/FIFO
* For troubleshooting of other areas of FPGA design, please see the Top Issues and Design Assistant areas of other available solutions centers.