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AR# 34979

Virtex-6 FPGA Design Assistant - Designing clocking structures in Virtex-6 FPGAs


The Virtex-6 clocking structure is made up of CMT tileseach containing two Mixed Mode Clock Managers (MMCMs) and different buffer types for routing clocks throughout the device. This Answer Record contains information on designing clocking structures for Virtex-6 FPGAs.
NOTE: This Answer Record is a part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963). The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.


The Mixed Mode Clock Manager (MMCM), available in the Virtex-6 device family, allows you to perform the following:
  • Clock Frequency Synthesis
  • Phase Alignment/Phase Shifting
  • Duty Cycle Modification
  • Cleaning up a noisy clock

When using the MMCM in your design, Xilinx recommends that you use the Clocking Wizard, available in the CORE Generator software, to help you generate your MMCM based on your needs using an easy to use Wizard.For more information about this Wizard, including how to access the Clocking Wizard,see (Xilinx Answer 36990).
Clock Buffers
If you want to setup clock regions, or control clock usage with an enable or select signal, there are a couple of options for buffers that you can use inside your device.For additional information on the types of buffers available in the Virtex-6 family, refer to (Xilinx Answer 36991).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A

Associated Answer Records

AR# 34979
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
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