My design has some bi-directional differential IOBs that are behaving strangely. First, the placer did not place the differential pairs into paired sites and I had to lock them down. Everything seemed to run okay at that point, but BitGen fails with the following error:
"ERROR:Bitgen - Could not find programming information for I/O standard
DIFF_SSTL18_II drive=-1, slew=*, master=*. The programming of the output
buffers will not be correct."
Next, I have noticed that the IOB pair is made up of one IOBS (slave)and one IOB, instead of an IOBM (master). This cannot be right.
Is this a known problem and is there a work-around?
This problem has been seen in a design where the data path of the OBUFTDS was driven by GND, causing some constant optimization behavior that corrupted the configuration of the IOB pair.
This problem has been fixed in ISE 12.1. In the meantime, to work around the issue, insert a LUT1 buffer between GND and the OBUFTDS input and apply an "S" property to prevent the optimization of the buffer. This prevents the constant optimization that is the root cause of the IOB pair corruption.
Example of LUT1 buffer instantiation in VHDL:
generic map (INIT => X"2")
port map( I0 => '0',
O => buffered_gnd );
Example of UCF property to block optimization of the buffer:
INST "buffered_gnd_lut" S;